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Toshiba Implements Its Largest Semiconductor Design to Date with Cadence Digital IC Flow
Toshiba and Toshiba Microelectronics Deploy New Cadence SoC
Encounter-Based Standard Design Flow to Achieve First Silicon Success
SAN JOSE, Calif.—(BUSINESS WIRE)—Oct. 27, 2004—
Cadence Design Systems, Inc. (NYSE:CDN)(Nasdaq:CDN) today
announced that Toshiba Corporation and Toshiba Microelectronics
Corporation successfully taped out a 24-million-gate chip using
Cadence(R) SoC Encounter(TM). The chip, with an end application in
digital consumer electronics, is Toshiba's largest to date, and was
designed using Toshiba's TC300 process for 90 nanometer technology.
As indicated by this successful tapeout, SoC Encounter is now
fully supported as the digital IC implementation platform of choice
for Toshiba's standard design environment. Toshiba released the first
version of this design environment in July to its worldwide internal
design community and it is being used in several design projects
already underway.
"Deploying Encounter's Physical Prototyping functionality in the
early stage of the design process was critical to helping us avoid
schedule delays for this design," said Takashi Yoshimori, Technology
Executive SoC-Design of Toshiba'sSemiconductor Company. "We see this
chip as one of the year's most important projects in the digital
consumer arena."
"Our mission is to provide high quality designs with shorter
turnaround time," said Kiyofumi Ochii, Senior Vice President of
Toshiba Microelectronics Corporation. "SoC Encounter helped us meet
our goal for this extremely challenging design by delivering speed,
capacity and quality of results with a fully integrated design flow
from prototyping through GDS."
To achieve the highest quality of silicon with the simplest design
flow, Toshiba used Cadence SoC Encounter physical implementation
technology and wires-first methodology. SoC Encounter's powerful
timing and signal integrity closure flow coupled with fast
turn-around-time helped Toshiba achieve First Silicon Success for this
scale of design.
"We are delighted to see Toshiba successfully implementing its
largest 90 nanometer design to date using SoC Encounter," said Wei-Jin
Dai, platform vice president, digital IC implementation, Cadence
Design Systems. "Toshiba is one of Cadence's most highly valued
customers and this tapeout underscores our ongoing commitment to
customer success as measured in quality silicon."
About Cadence
Cadence is the world's largest supplier of electronic design
technologies and engineering services. Cadence products and services
are used to accelerate and manage the design of semiconductors,
computer systems, networking equipment, telecommunications equipment,
consumer electronics, and other electronics based products. With
approximately 4,850 employees and 2003 revenues of approximately $1.1
billion, Cadence has sales offices, design centers, and research
facilities around the world. The company is headquartered in San Jose,
Calif., and trades on both the New York Stock Exchange and Nasdaq
under the symbol CDN. More information is available at
www.cadence.com.
Cadence, the Cadence logo and SoC Encounter are registered
trademarks of Cadence Design Systems, Inc. All other trademarks are
the property of their respective owners.
Contact:
Cadence Design Systems, Inc.
Judy Erkanat, 408-894-2302
jerkanat@cadence.com
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